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        <title>Lowyat.NET: Latest topics by msyafiq_m</title>
        <description></description>
        <link>http://forum.lowyat.net/</link>
        <lastBuildDate>Sun, 28 Jun 2026 09:30:25 +0800</lastBuildDate>
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            <title>Setting up a &amp;quot;Full HD Movie&amp;quot; Rig</title>
            <link>http://forum.lowyat.net/topic/890108</link>
            <description>A friend asked me to setup a PC for him, his main purpose is to watch HD movie on his Dell S2409W(he doesn&amp;#39;t play any games at all).&lt;br /&gt;Budget was not mentioned, as long as the money spent is worth it. So my questions are:&lt;br /&gt;&lt;br /&gt;1) Is there any motherboard with integrated GC that can support Full HD?&lt;br /&gt;&lt;br /&gt;If (1) is yes:&lt;br /&gt;&lt;br /&gt;2a) As the LCD comes with a HDMI connector, can any of you suggest a board that provide this output?&lt;br /&gt;&lt;br /&gt;If (1) is no:&lt;br /&gt;&lt;br /&gt;2b) Please suggest the minimum GC required to achieve his objective&lt;br /&gt;&lt;br /&gt;Thanks.&lt;br /&gt;&lt;br /&gt;</description>
            <author>msyafiq_m</author>
            <category>Hardware</category>
            <pubDate>Mon, 29 Dec 2008 20:49:58 +0800</pubDate>
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        <item>
            <title>ASIC Design(Computer Architecture Design)</title>
            <link>http://forum.lowyat.net/topic/762580</link>
            <description>Hi,&lt;br /&gt;&lt;br /&gt;Currently in my 3rd year in IIUM, doing Computer Engineering. This semester, i&amp;#39;m taking Computer Architecture and System Design(both theory and Verilog/VHDL language studies). Anyone else taking the course or had taken it before? Let&amp;#39;s share our experiences and knowledge on this course.. &lt;!--emo&amp;:)--&gt;&lt;img src='http://static.lowyat.net/style_emoticons/default/smile.gif' border='0' style='vertical-align:middle' alt='smile.gif' /&gt;&lt;!--endemo--&gt; &lt;br /&gt;&lt;br /&gt;Ok,let me start with a question that needs some explanation. Refer to the next two codes:&lt;br /&gt;&lt;br /&gt;1. The following generates a mux:&lt;br /&gt;&lt;br /&gt;reg out, sel, a, b;&lt;br /&gt;always @ (sel or a or b)&lt;br /&gt;if(sel)&lt;br /&gt;          out = a;&lt;br /&gt;else out = b;&lt;br /&gt;&lt;br /&gt;2. The following infers a latch:&lt;br /&gt;&lt;br /&gt;always @ (sel or a or b)&lt;br /&gt;if(sel)&lt;br /&gt;          out = a;&lt;br /&gt;&lt;br /&gt;Through my reading, i was being informed that the 2nd case happen because the storage device is being inferred.But i don&amp;#39;t actually get what does it mean by being inferred(refering to the 2nd case)? Anyone care to explain?&lt;br /&gt;&lt;br /&gt;[addedon]August 12, 2008, 9:32 pm[/addedon]Anyone? I believe there must be some other LYN&amp;#39;ers with experience in Verilog and VHDL. Maybe can share your experience in terms of software use for simulation and synthesis.As for myself, currently undergoing certification for Synopsys. &lt;br /&gt;&lt;br /&gt;(&lt;!--emo&amp;^_^--&gt;&lt;img src='http://static.lowyat.net/style_emoticons/default/happy.gif' border='0' style='vertical-align:middle' alt='happy.gif' /&gt;&lt;!--endemo--&gt;)</description>
            <author>msyafiq_m</author>
            <category>Education Essentials</category>
            <pubDate>Sat, 09 Aug 2008 13:55:07 +0800</pubDate>
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